Junction barrier schottky diodes with current surge capability

ABSTRACT

An electronic device includes a silicon carbide drift region having a first conductivity type, a Schottky contact on the drift region, and a plurality of junction barrier Schottky (JBS) regions at a surface of the drift region adjacent the Schottky contact. The JBS regions have a second conductivity type opposite the first conductivity type and have a first spacing between adjacent ones of the JBS regions. The device further includes a plurality of surge protection subregions having the second conductivity type. Each of the surge protection subregions has a second spacing between adjacent ones of the surge protection subregions that is less than the first spacing.

CLAIM OF PRIORITY

The present application is a continuation of U.S. patent applicationSer. No. 13/547,014, entitled JUNCTION BARRIER SCHOTTKY DIODES WITHCURRENT SURGE CAPABILITY, which was filed Jul. 11, 2012, which was acontinuation of U.S. Pat. No. 8,232,558, entitled JUNCTION BARRIERSCHOTTKY DIODES WITH CURRENT SURGE CAPABILITY, which issued on Jul. 31,2012, the disclosure of which is hereby incorporated herein by referenceas if set forth fully.

FIELD OF THE INVENTION

The present invention relates to semiconductor devices and thefabrication of semiconductor devices and more particularly, to JunctionBarrier Schottky (JBS) diodes, and the fabrication of such diodes.

BACKGROUND

High voltage silicon carbide (SiC) Schottky diodes, which may havevoltage blocking ratings between, for example, about 600V and about 2.5kV, are expected to compete with silicon PIN diodes having similarvoltage ratings. Such diodes may handle as much as about 100 amps ormore of forward current, depending on their active area design. Highvoltage Schottky diodes have a number of important applications,particularly in the field of power conditioning, distribution andcontrol.

An important characteristic of a SiC Schottky diode in such applicationsis its switching speed. Silicon-based PIN devices typically exhibitrelatively poor switching speeds. A silicon PIN diode may have a maximumswitching speed of approximately 20 kHz, depending on its voltagerating. In contrast, silicon carbide-based Schottky devices aretheoretically capable of much higher switching speeds, for example, inexcess of about 100 times better than silicon. In addition, siliconcarbide devices may be capable of handling a higher current density thansilicon devices.

A conventional SiC Schottky diode structure has an n-type SiC substrateon which an n− epitaxial layer, which functions as a drift region, isformed. The device typically includes a Schottky contact formed directlyon the n− layer. A junction termination region, such as a guard ringand/or p-type JTE (junction termination extension) region, is typicallyformed to surround the Schottky junction active region.

The purpose of junction termination region is to reduce or preventelectric field crowding at the edges of the Schottky junction, and toreduce or prevent the depletion region from interacting with the surfaceof the device. Surface effects may cause the depletion region to spreadunevenly, which may adversely affect the breakdown voltage of thedevice. Other termination techniques include field plates and floatingfield rings that may be more strongly influenced by surface effects. Achannel stop region may also be formed by implantation of n-type dopantsin order to prevent the depletion region from extending to the edge ofthe device.

Regardless of the type of termination used, the Schottky diode willtypically fail if a large enough reverse voltage is applied to thejunction. Such failures are generally catastrophic, and may damage ordestroy the device. Furthermore, even before the junction has failed, aSchottky diode may experience large reverse leakage currents. In orderto reduce such leakage currents, the junction barrier Schottky (JBS)diode was developed. JBS diodes are sometimes referred to as MergedPIN—Schottky (MPS) diodes. A conventional JBS diode 10 is illustrated inFIG. 1. As shown therein, a conventional JBS diode includes an n-typesubstrate 12 on which an n− drift layer 14 is formed. A plurality of p+regions 16 are formed, typically by ion implantation, in the surface ofthe n− drift layer 14. A metal anode contact 18 is formed on the surfaceof the n− drift layer 14 in contact with both the n− drift layer 14 andthe p+ regions 16. The anode contact 18 forms a Schottky junction withthe exposed portions of the drift layer 14, and may form an ohmiccontact with the p+ regions 16. A cathode contact 20 is formed on thesubstrate 12. Silicon carbide-based JBS diodes are described, forexample, in U.S. Pat. Nos. 6,104,043 and 6,524,900.

In forward operation, the junction J1 between the anode contact 18 andthe drift layer 14 turns on before the junction J2 between the p+regions 16 and the drift layer 14. Thus, at low forward voltages, thedevice exhibits Schottky diode behavior. That is, current transport inthe device is dominated by majority carriers (electrons) injected acrossthe Schottky junction J1 at low forward voltages. As there may be nominority carrier injection (and thus no minority charge storage) in thedevice at normal operating voltages, JBS diodes have fast switchingspeeds characteristic of Schottky diodes.

Under reverse bias conditions, however, the depletion regions formed bythe PN junctions J2 between the p+ regions 16 and the drift layer 14expand to block reverse current through the device 10, protecting theSchottky junction J1 and limiting reverse leakage current in the device10. Thus, in reverse bias, the JBS diode 10 behaves like a PIN diode.The voltage blocking ability of the device 10 is typically determined bythe thickness and doping of the drift layer 14 and the design of theedge termination.

One problem commonly encountered with silicon carbide JBS diodes istheir ability to handle current surges. Silicon carbide JBS Schottkydiodes are typically designed for use in power switching applications,such as power factor control (PFC) in high voltage distribution systems.In such applications, surge currents can be experienced during power onand/or after line cycle dropouts. When a current surge occurs,substantial power can be dissipated in the diode, which can result incatastrophic failure of the device due to thermal runaway.

A JBS Schottky diode can be designed so that the the junction J2 betweenthe p+ regions 16 and the drift layer 14 turns on under high currentconditions, resulting in an injection of miority carriers (holes) acrossthe junction J2 into the drift layer 14. This injection of minoritycarriers modulates the conductivity of the drift layer 14, reducing theresistance to current and therefore reducing the potential for failureof the device as a result of the current surge. However, designing thep+ regions 16 so that the junction J2 turns on at high currents canundesirably increase the on-state resistance of the device at lowercurrents.

SUMMARY

An electronic device according to some embodiments includes a siliconcarbide drift region having a first conductivity type, a Schottkycontact on the drift region, and a plurality of junction barrierSchottky (JBS) regions at a surface of the drift region adjacent theSchottky contact. The JBS regions have a second conductivity typeopposite the first conductivity type and have a first width and a firstspacing between adjacent ones of the JBS regions. The device furtherincludes a surge protection region at the surface of the drift regionadjacent the Schottky contact. The surge protection region has a secondwidth greater than the first width and includes a plurality of surgeprotection subregions having the second conductivity type. Each of thesurge protection subregions has a third width less than the first widthand has a second spacing between adjacent ones of the surge protectionsubregions that may be less than the first spacing between adjacent onesof the JBS regions.

The first spacing may be about 4 μm to about 6 μm and the second spacingmay be about 1 μm to about 3 μm. The first width may be about 1 μm toabout 3 μm and the third width may be about 1 μm to about 3 μm.

The surge protection subregions may extend into the drift layer from thesurface of the drift layer by a depth of about 0.3 μm to about 0.5 μm. Adoping level of the drift region may be about 5×10¹⁴ cm⁻³ to about1×10¹⁶ cm⁻³.

The first spacing, the second spacing and the third width are configuredsuch that a voltage drop from a surface of the drift layer to a centerof a junction between one of the surge protection subregions and thedrift region may be sufficient to cause the junction to become forwardbiased at a forward current that is higher than a rated current of theSchottky diode so as to provide a current surge handling ability in theSchottky diode.

An interface between the Schottky contact and the surge protectionsubregions may be an ohmic contact.

The drift layer may include 4H-SiC. The drift layer may have a dopinglevel of about 5×10¹⁵ cm⁻³ to 1 10¹⁶ cm⁻³, and the current surge controlsubregions may have a doping level greater than 5×10¹⁸ cm⁻³.

A portion of the drift region beneath the surge protection regions mayhave a higher electric potential than a portion of the drift regionbeneath the JBS regions in response to a forward voltage applied to theSchottky contact.

The device may further include a plurality of current surge controlregions in the drift layer adjacent the Schottky contact.

The first conductivity type may include n-type and the secondconductivity type may include p-type.

The surge control subregions include a plurality of trenches in thedrift region and a plurality of doped regions in the drift layerextending beneath respective ones of the plurality of trenches.

The surge protection subregions may define vertical current paths in thedrift region between respective ones of the surge protection subregions,a depth of the surge protection regions may be defined by a depth of thetrenches and a depth of the doped regions.

Methods of forming a Schottky diode according to some embodimentsinclude forming a plurality of junction barrier Schottky (JBS) regionsat a surface of a silicon carbide drift region having a firstconductivity type, the plurality of JBS regions having a secondconductivity type opposite the first conductivity type and having afirst spacing between adjacent ones of the JBS regions. The methodsfurther include forming a surge protection region at the surface of thedrift region adjacent the Schottky contact, the surge protection regionincluding a plurality of surge protection subregions having the secondconductivity type and each of the surge protection subregions having asecond spacing between adjacent ones of the surge protection subregionsthat may be less than the first spacing between adjacent ones of the JBSregions. A Schottky contact is formed on the drift region.

The first spacing may be about 4 μm to about 6 μm and the second spacingmay be about 1 μm to about 3 μm.

Forming the plurality of JBS regions and forming the surge protectionregion may include selectively implanting dopant ions of the secondconductivity into the drift layer, and annealing the implanted ions at atemperature greater than 1700° C.

The methods may further include forming a graphite coating on the driftlayer including the implanted ions, annealing the implanted ions mayinclude annealing the graphite coating.

The methods may further include etching a plurality of trenches in thedrift layer before implanting the ions, implanting the ions may includeimplanting the ions into the plurality of trenches.

Forming the Schottky contact on the drift region may include forming theSchottky contact to the drift region and an ohmic contact to the surgeprotection subregions using a single metal.

An electronic device according to further embodiments includes a siliconcarbide drift region having a first conductivity type, a Schottkycontact on the drift region, and a plurality of junction barrierSchottky (JBS) regions at a surface of the drift region adjacent theSchottky contact. The plurality of JBS regions have a secondconductivity type opposite the first conductivity type and have a firstspacing between adjacent ones of the JBS regions. The device furtherincludes a plurality of surge protection subregions having the secondconductivity type. Each of the surge protection subregions has a secondspacing between adjacent ones of the surge protection subregions that isless than the first spacing.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included to provide a furtherunderstanding of the invention and are incorporated in and constitute apart of this application, illustrate certain embodiment(s) of theinvention. In the drawings:

FIG. 1 is a cross-sectional view of a conventional JBS diode.

FIG. 2 is a top view of a JBS diode including surge protection regions.

FIG. 3 is a cross-sectional view of a JBS diode including a surgeprotection region.

FIG. 4 is a cross-sectional view of a JBS diode according to someembodiments.

FIG. 5 is a detail view illustrating additional aspects of the JBS diodeof FIG. 4.

FIG. 6 is a cross-sectional view of an intermediate structure formedduring fabrication of a JBS diode according to some embodiments.

FIG. 7A is a cross-sectional view of an intermediate structure formedduring fabrication of a JBS diode according to further embodiments.

FIG. 7B is a cross-sectional view of a JBS diode according to furtherembodiments.

FIG. 8A illustrates a simulated device structure and simulation resultsfor a device according to some embodiments.

FIG. 8B illustrates a simulated device structure and simulation resultsfor a comparison device.

FIG. 9 illustrates simulated current versus voltage characteristics fora device according to some embodiments.

FIG. 10 illustrates simulated hole concentration characteristics for adevice according to some embodiments.

FIG. 11 illustrates simulated voltage potential characteristics for adevice according to some embodiments.

FIG. 12 illustrates an implantation mask pattern that can be usedaccording to some embodiments.

DETAILED DESCRIPTION OF EMBODIMENTS OF THE INVENTION

Embodiments of the present invention now will be described more fullyhereinafter with reference to the accompanying drawings, in whichembodiments of the invention are shown. This invention may, however, beembodied in many different forms and should not be construed as limitedto the embodiments set forth herein. Rather, these embodiments areprovided so that this disclosure will be thorough and complete, and willfully convey the scope of the invention to those skilled in the art.Like numbers refer to like elements throughout.

It will be understood that, although the terms first, second, etc. maybe used herein to describe various elements, these elements should notbe limited by these terms. These terms are only used to distinguish oneelement from another. For example, a first element could be termed asecond element, and, similarly, a second element could be termed a firstelement, without departing from the scope of the present invention. Asused herein, the term “and/or” includes any and all combinations of oneor more of the associated listed items.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the invention. Asused herein, the singular forms “a”, “an” and “the” are intended toinclude the plural forms as well, unless the context clearly indicatesotherwise. It will be further understood that the terms “comprises”“comprising,” “includes” and/or “including” when used herein, specifythe presence of stated features, integers, steps, operations, elements,and/or components, but do not preclude the presence or addition of oneor more other features, integers, steps, operations, elements,components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this invention belongs. It will befurther understood that terms used herein should be interpreted ashaving a meaning that is consistent with their meaning in the context ofthis specification and the relevant art and will not be interpreted inan idealized or overly formal sense unless expressly so defined herein.

It will be understood that when an element such as a layer, region orsubstrate is referred to as being “on” or extending “onto” anotherelement, it can be directly on or extend directly onto the other elementor intervening elements may also be present. In contrast, when anelement is referred to as being “directly on” or extending “directlyonto” another element, there are no intervening elements present. Itwill also be understood that when an element is referred to as being“connected” or “coupled” to another element, it can be directlyconnected or coupled to the other element or intervening elements may bepresent. In contrast, when an element is referred to as being “directlyconnected” or “directly coupled” to another element, there are nointervening elements present.

Relative terms such as “below” or “above” or “upper” or “lower” or“horizontal” or “lateral” or “vertical” may be used herein to describe arelationship of one element, layer or region to another element, layeror region as illustrated in the figures. It will be understood thatthese terms are intended to encompass different orientations of thedevice in addition to the orientation depicted in the figures.

Embodiments of the invention are described herein with reference tocross-section illustrations that are schematic illustrations ofidealized embodiments (and intermediate structures) of the invention.The thickness of layers and regions in the drawings may be exaggeratedfor clarity. Additionally, variations from the shapes of theillustrations as a result, for example, of manufacturing techniquesand/or tolerances, are to be expected. Thus, embodiments of theinvention should not be construed as limited to the particular shapes ofregions illustrated herein but are to include deviations in shapes thatresult, for example, from manufacturing. For example, an implantedregion illustrated as a rectangle will, typically, have rounded orcurved features and/or a gradient of implant concentration at its edgesrather than a discrete change from implanted to non-implanted region.Likewise, a buried region formed by implantation may result in someimplantation in the region between the buried region and the surfacethrough which the implantation takes place. Thus, the regionsillustrated in the figures are schematic in nature and their shapes arenot intended to illustrate the actual shape of a region of a device andare not intended to limit the scope of the invention.

Some embodiments of the invention are described with reference tosemiconductor layers and/or regions which are characterized as having aconductivity type such as n-type or p-type, which refers to the majoritycarrier concentration in the layer and/or region. Thus, n-type materialhas a majority equilibrium concentration of negatively chargedelectrons, while p-type material has a majority equilibriumconcentration of positively charged holes. Some material may bedesignated with a “+” or “−” (as in n+, n−, p+, p−, n−−, p++, p−−, orthe like), to indicate a relatively larger (“+”) or smaller (“−”)concentration of majority carriers compared to another layer or region.However, such notation does not imply the existence of a particularconcentration of majority or minority carriers in a layer or region.

FIG. 2 is a top view of a Schottky diode structure 100 in which currentsurges are handled by sizing and doping the p+ regions so that they willturn on at high current densities and inject minority carriers into thedrift layer 14. Similar diodes are disclosed in U.S. Publication No.2008/0029838 entitled “Semiconductor Devices Including Schottky DiodesWith Controlled Breakdown And Methods Of Fabricating Same”, which isassigned to the assignee of the present invention, the disclosure ofwhich is incorporated herein by reference.

Referring to FIG. 2, the diode 100 includes a drift layer 114 having anupper surface in which a plurality of JBS regions 130 of oppositeconductivity type from the drift layer 114 are formed as stripe-shapedregions in the drift layer 114. The JBS regions 130 may be formed, forexample, by ion implantation of p-type dopants such as boron and/oraluminum into the drift layer 114 at a concentration of about 1×10¹⁷ toabout 1×10¹⁸ cm⁻³, and may extend to a depth of about 0.3 to about 0.5μm beneath the surface of the drift layer 114.

One or more surge protection regions 116 is also provided in the driftlayer 114. The surge protection regions 116 may be formed, for example,by ion implantation of p-type dopants such as boron and/or aluminum intothe drift layer 114 at a concentration of about 1×10¹⁸ to about 1×10¹⁹cm⁻³, and may extend to a depth of about 0.3 to about 0.5 μm beneath thesurface of the drift layer 114.

The JBS regions 130 expose portions 114A of the surface of the driftlayer 114 and that extend across an active region 110 of the drift layer114 (except for the exposed portions 114A of the drift layer and theheavily doped regions 116). A metal Schottky contact 118 (FIG. 3) coversthe drift layer 114 and is in contact with the exposed portions 114A ofthe drift layer 114 as well as the JBS regions 130 and the surgeprotection regions 116. As used herein, the term “active region” refersto the two dimensional area of the device in which the Schottky metalcontacts the drift layer and includes the exposed portions 114A of thedrift layer 114, the JBS regions 130 and the surge protection regions116. Accordingly, the active region includes the Schottky junction areabut does not include, for example, the edge termination region.

FIG. 3 is a cross-sectional illustration of the diode 100 takengenerally along lines A-A′ of FIG. 2. As seen in FIG. 3, the diode 100includes a substrate 112 on which the drift layer 114 is formed. Thesurge protection regions 116 may be formed as an implanted region withinthe drift layer 114. Similarly, the JBS regions 130 may be formed asimplanted regions in the drift layer 114. As the surge protectionregions 116 and the JBS regions 130 have an opposite conductivity typefrom the drift layer 114, the JBS regions 130 form a p-n junction J3with the drift layer 114, while the heavily doped regions 116 form a p-njunction J5 with the drift layer 114.

An anode contact 118 on the surface of the drift layer 114 forms aSchottky junction J4 with the exposed portions 114A of the drift layer114 between adjacent lightly doped regions 130 and/or between a JBSregion 130 and the surge protection region 116. The anode contact 118may include a metal, such as aluminum, titanium and/or nickel, that mayform an ohmic contact with the surge protection region 116, whileforming a Schottky contact with the drift layer 114. As illustrated inFIG. 3, the anode contact 118 can include a first portion 118A thatforms an ohmic contact on the surge protection region 116 and a secondportion 118B. that forms a Schottky contact with the drift layer 114. Inparticular, the second portion 118B may be formed to cover the firstportion 118A of the anode contact 118. The first portion 118A mayinclude, for example, aluminum, titanium and/or nickel, while the secondportion 118B may include, for example, aluminum, titanium and/or nickel.

A cathode contact 120 is formed on a side of the substrate 112 oppositethe drift layer 114. The cathode contact 120 may include a metal, suchas nickel, that is capable of forming an ohmic contact to n-type siliconcarbide.

In forward operation, the junction J4 between the anode contact 118 andthe exposed portions 114A of the drift layer 114 turns on before thejunction J5 between the surge protection region 116 and the drift layer114. Thus, at low forward voltages, the device exhibits Schottky diodebehavior. That is, at low forward voltages, the operation of the diode100 is dominated by the injection of majority carriers across theSchottky junction J4. Due to the absence of minority carrier injectionunder normal operating conditions, the diode 100 may have a very fastswitching capability, which is characteristic of Schottky diodes ingeneral.

The surge protection region 116 may be designed to begin to conduct at aforward voltage that is higher than the turn-on voltage of the Schottkyjunction J4. Thus, in the event of a current surge that causes theforward voltage of the diode 100 to increase, the p-n junction J5 willbegin to conduct. Once the p-n junction J5 begins to conduct, theoperation of the diode 100 becomes dominated by the injection andrecombination of minority carriers across the p-n junction J5. In thatcase, the on-state resistance of the diode may decrease, which maydecrease the amount of power dissipated by the diode 100 for a givenlevel of current. Thus, turn-on of the p-n junction J5 when the forwardvoltage of the diode 100 increases may reduce and/or prevent forwardcurrent runaway in the diode 100.

In forward operation, a forward current If flows vertically downwardadjacent the JBS regions 130 and the surge protection region 116.Current also flows horizontally across the face of the surge protectionregion 116. Turn-on of the p-n junction J5 occurs when a voltage drop □Vfrom the surface 114A of the drift region to the middle of the surgeprotection region 116 exceeds the built-in voltage of the p-n junctionJ5. Thus, for a given level of doping in the drift region 114, the surgeprotection region 116 may be designed to have at least a minimum lateralwidth (or minimum extent) to cause the p-n junction J5 to turn on at adesired turn-on level of the forward current If.

Some embodiments of the invention arise from a realization that thedesired voltage drop can be obtained by methods other than simplyincreasing the lateral width of the surge protection region 116, whichcan undesirably increase the on-state resistance of the device 100.

For example, FIG. 4 illustrates embodiments in which a surge protectionregion 216 is formed using a plurality of subregions 226 having adefined depth, width, spacing and doping to provide both reverse biasprotection as well as surge current protection.

In particular, FIG. 4 is a cross-sectional view of a diode 200 accordingto some embodiments of the invention. The diode 200 includes a driftlayer 214 having an upper surface in which a plurality of JBS regions230 of opposite conductivity type from the drift layer 214 are formed.

The drift layer 214 may be formed, for example, from n-type siliconcarbide of the 2H, 4H, 6H, 3C and/or 15R polytype having a dopantconcentration of about 5×10¹⁴ to about 1×10¹⁶ cm⁻³, depending on designrequirements for voltage blocking and on-resistance for the diode 200.Other types of semiconductor materials, such as GaN, GaAs, silicon orgermanium may be used. In particular embodiments, the drift layer 214includes 4H-SiC doped with n-type dopants at a concentration of about5×10^(15 cm) ⁻³. The JBS regions 230 may be formed, for example, by ionimplantation of p-type dopants such as boron and/or aluminum into thedrift layer 214 at a concentration of about 1×10¹⁸ cm⁻³ to 1×10^(19 cm)⁻³, and may extend to a depth of about 0.3 to about 0.5 μm beneath thesurface of the drift layer 214. In particular embodiments, the JBSregions 230 may be doped with p-type dopants at a concentration of about5×10¹⁸ cm⁻³.

The surge protection region 216 includes a plurality of subregions 226in the drift layer 214. The subregions 226 may be formed, for example,by ion implantation of p-type dopants such as boron and/or aluminum intothe drift layer 214 at a concentration of about 1×10¹⁸ to about 1×10¹⁹cm⁻³, and may extend to a depth of about 0.3 to about 0.5 μm beneath thesurface of the drift layer 114. In particular embodiments, thesubregions 116 may be doped at a dopant concentration of about 5×10¹⁸cm⁻³, and may extend to a depth of about 0.5 pm beneath the surface ofthe drift layer 214. Each of the subregions 226 forms a p-n junction J6with the drift region 214. In some embodiments, the subregions 226 canbe implanted at the same time as the JBS regions 230. Accordingly, thesubregions 226 can have the same depth and doping profile as the JBSregions 230. However, in other embodiments, the subregions 226 can beformed in a different process than the JBS regions 230 and can have adifferent depth and/or doping profile than the JBS regions 230.

Activation of the implanted dopants in the JBS regions 230 and thesubregions 226 can be performed by annealing the structure including thesubstrate 212, the drift layer 214 and the implanted regions at asufficiently high temperature. In some embodiments, a graphite coatingmay be formed on the surface of the drift region 214 prior to implantactivation. The graphite coating may be removed after annealing theimplanted ions. The graphite coating may be crystallized beforeannealing the implanted ions.

The implanted ions may be annealed at a temperature greater than 1700°C., and in some embodiments greater than 1800° C.

For example, referring to FIG. 6, the implanted dopants in the JBSregions 230 and the subregions 226 may be activated by annealing thestructure at a temperature of about 1600° C. or more with a silicon overpressure and/or covered by an encapsulation layer such as a graphitefilm. In some embodiments, the implants may be activated by annealing ata temperature greater than about 1700° C. using a graphite coating.

A high temperature activation anneal (e.g. 1700° C. or more) may enhancethe activation of the threshold adjustment ions, as well as annealing ofdefects in the channel region 40. However, such a high temperatureanneal may damage the surface of the silicon carbide drift layer 16.

To reduce damage that may result from a high temperature anneal, agraphite coating 250 may be formed on the surface of the structure priorto formation of the metal contacts thereto. That is, prior to annealingthe structure to activate the implanted ions, a graphite coating 250 maybe applied to the top/front side of the drift layer 214 in order toprotect the surface of the structure during the anneal. The graphitecoating 250 may be applied by a conventional resist coating method andmay have a thickness that is sufficient to protect the underlying SiClayers during a high temperature anneal. The graphite coating 250 mayhave a thickness of about 1 μm. Prior to the anneal, the graphitecoating 250 may be heated to form a crystalline coating on the driftlayer 214. The implanted ions may be activated by a thermal anneal thatmay be performed, for example, in an inert gas at a temperature of about1700° C. or greater. In particular the thermal anneal may be performedat a temperature of about 1850° C. in argon for 5 minutes. The graphitecoating 250 may help to protect the surface of the drift layer 214during the high temperature anneal.

The graphite coating 250 may then be removed, for example, by ashing andthermal oxidation.

In addition to activating the implanted ions, a high temperature annealwith a graphite coating can facilitate the formation of an ohmic contactto the subregions 216. That is, without wishing to be bound by anyparticular theory of operation, it is presently believed that p-typedopants, such as Al ions, in the surge protection subregions 226accumulate at the surface of the subregions 226 during a hightemperature anneal. When a metal, such as titanium, is deposited ontothe drift layer 214 as the anode contact 218, the metal may desirablyform an ohmic contact with the underlying subregions 226. Forming anohmic contact between the anode metal 218 and the subregions 226 mayenhance the overcurrent protection provided by the surge protectionregion 216 by making it easier for the p-n junction J6 to turn on at thedesired level of forward current. Futhermore, in some embodiments, itmay be possible to use only a single metal for the anode contact thatforms a Schottky contact to the drift region 214 as well as an ohmiccontact to the subregions 226, which can reduce manufacturing timeand/or expense.

The JBS regions 230 shown in the embodiments of FIG. 4 may be providedas spaced apart striped regions that expose portions 214A of the surfaceof the drift layer 214 and that extend across an active region of thedrift layer 214 (except for the exposed portions 214A of the drift layerand the subregions 226). A metal Schottky contact 218 covers the driftlayer 214 and is in contact with the exposed portions 214A of the driftlayer 214 as well as the JBS regions 230 and the subregions 226.

The diode 200 may include an edge termination region (not shown)surrounding the active region 110 of the diode 100. The edge terminationregion may include a junction termination extension (JTE) region, fieldrings, field plates, guard rings, and/or a combination of the foregoingor other terminations.

A cathode contact 220 is formed on a side of the substrate 212 oppositethe drift layer 214. The cathode contact 220 may include a metal, suchas nickel, that is capable of forming an ohmic contact to n-type siliconcarbide.

In forward operation, a forward current If flows vertically downwardadjacent the JBS regions 230 and the subregions 226. Current also flowshorizontally across the face of the surge protection regions 226.Turn-on of the p-n junction J6 between a subregion 226 and the driftlayer 214 occurs when a voltage drop □V from the surface 214A of thedrift region to the middle of the subregion 226 exceeds the built-involtage of the p-n junction J6. However, a portion of the voltage drop□V can occur in the vertical current path 226A between adjacentsubregions 226. The resistance of a vertical current path 226A is afunction of the length and width of the vertical current path 226A andthe surface doping of the drift region 214. Accordingly, someembodiments control the length and width of the vertical current path226A as well as the surface doping of the drift region 214 so thatbipolar conduction between the subregions 226 and the drift region 214across the junction J6 occurs at a desired level of forward current.

Some further aspects of the diode 200 are shown in FIG. 5, which is across-sectional detail view of portions of the diode 200. In particular,as illustrated in FIG. 5, the subregions 226 may have a width W, aspacing S and a depth L. The JBS regions 230 may have a width W_(JBS)and a spacing S_(JBS). The JBS regions 230 may be spaced apart from thesurge protection region 216 by the JBS spacing S_(JBS). The resistanceof the vertical current paths 226A between adjacent subregions 226 canbe expressed as:

$\begin{matrix}{R = {\rho \; \frac{L}{S}}} & (1)\end{matrix}$

That is, the resistance of the vertical current paths is proportional tothe depth L of the subregions 226 and is inversely proportional to thespacing S between adjacent subregions 226. Accordingly, a desiredvoltage drop □V can be obtained by making the subregions 226 deeperand/or more closely spaced. Making the subregions 226 deeper may presenta challenge due to the limits of ion implantation technology. Inparticular, using ion implantation alone, it may be difficult to formthe subregions 226 to have a depth L of more than 0.5 μm. Thislimitation is addressed in further embodiments, described in detailbelow.

However, the spacing S between adjacent subregions 226 can be reducedthrough photolithography so that the resistance of the vertical currentpaths 226A can be increased to the point that conduction of the p-njunction J6 can begin at a desired level of forward current If.

In some embodiments, the depth L of the subregions 226 may be from 0.3to 0.5 μm. The width W of the subregions 226 may be from about 1 μm toabout 3 μm. The spacing S between adjacent subregions 226 may be fromabout 1 μm to about 3 μm. The width W_(JBS) of the JBS regions 230 maybe from about 1 μm to about 3 μm. The spacing S_(JBS) between adjacentJBS regions 230 and/or between a JBS region 230 and the current surgeregion 216 may be from about 4 μm to about 6 μm, or about 2 to 4 timesthe spacing S between adjacent subregions 226. The width of the surgeprotection region 216 may be about 10 μm or more.

FIGS. 7A and 7B illustrate structures/methods according to furtherembodiments. As shown therein, subregions 326 of a surge protectionregion 316 can be formed by etching trenches 320 into the drift layer214. The subregions 326 can be etched, for example, using a dry etchtechnique such as plasma etching, Inductively Coupled Plasma (ICP),Electron Cyclotron Resonance (ECR), etc., using a fluroine basedchemistry such as SF₆, CHF₃, etc.

The trenches 320 can be etched to a depth d of from about 0.3 μm toabout 1 μm. After trench formation, ions 310, for example, p-type ionssuch as aluminum and/or boron, can be implanted into the trenches 320through an implant mask 315 to form the subregions 326. The ions can beimplanted, for example, at a dose of 1×10¹⁵ cm⁻², and an energy of up to300 keV. The ions can be implanted with a tilt angle of 30° so that thesidewalls of the trenches 320 are implanted. Furthermore, theimplantation can be performed at a temperature of 25° C. As will beappreciated, the depth L of the vertical channel 326A between adjacentsubregions 326 is then the sum of the depth d of the trenches 320 andthe junction depth of the implants. A longer vertical channel 326A witha correspondingly higher resistance can thereby be obtained.

Furthermore, the anode contact 218 can penetrate into the trenches 320to form ohmic contacts to the subregions 326 with a larger surface area,and hence lower resistance. The resulting device 300, including an anodecontact 220 on the substrate 212, is shown in FIG. 7B.

FIGS. 8A and 8B illustrate simulation results for diodes similar to thediodes illustrated in FIGS. 4 and 3, respectively. In particular, FIGS.8A and 88 graphically illustrate hole concentrations in the devicesunder surge current conditions at a forward voltage drop of 5.2V. Forexample, FIG. 8A illustrates a structure 200A including a drift region214. A JBS region 230 and a plurality of surge protection subregions 226are formed at a surface of the drift region 214. Vertical current paths226A are defined between adjacent ones of the surge protectionsubregions 226. Also plotted in FIG. 8A is a line 410 that indicates theposition of the depletion region boundary within the structure 200A.FIG. 8B illustrates a structure 100A including a drift region 114. A JBSregion 130 and a single surge protection region 116 are formed at asurface of the drift region 114. The line 420 in FIG. 8B indicates theposition of the depletion region boundary in the structure 100A.

As shown in FIGS. 8A and 8B, holes can be injected from the subregions226 in the device 200A of FIG. 8A and from the surge protection region116 in the device 100A of FIG. 8B. However, a higher hole concentrationcan be injected from the central subregion 226′ in the device 200A inFIG. 8A than from the surge protection region 116 in the device 100A inFIG. 833.

FIG. 9 illustrates simulated current versus voltage for the structures200A and 100A shown in FIGS. 8A and 8B, respectively. In particular,FIG. 9 indicates that a current begins in both devices at a voltage ofapproximately 4.8V. However, the device 200A appears to have a lowerresistance during surge current conditions than the device 100A, asindicated by a higher slope of the I-V curve at voltages exceeding 4.8V.It will be appreciated that in-the simulation, the voltage wasreferenced from the cathode to the anode. Thus, forward bias and forwardcurrent were assigned negative polarities.

FIG. 10 is a graph of simulated hole concentration versus lateralposition in the devices 200A and 100A illustrated in FIGS. 8A and 8B,respectively. In particular, curve 442 shows the simulated holeconcentration versus position for the device structure 100A of FIG. 8B,while curve 444 shows the simulated hole concentration versus positionfor the device structure 200A of FIG. 8A. The simulations predict higherhole concentrations for the device structure 200A of FIG. 8A.

FIG. 11 is a graph of simulated potential versus lateral position in thedevices 200A and 100A illustrated in FIGS. 8A and 8B, respectively. Inparticular, curve 452 shows the simulated potential versus position forthe device structure 100A of FIG. 8B, while curve 454 shows thesimulated potential versus position for the device structure 200A ofFIG. 8A. The simulations predict local increases in potential over thevertical current paths 226A between adjacent subregions 226 for thedevice structure 200A of FIG. 8A. Furthermore, in the device structure200A, a portion of the drift region beneath the surge protectionsubregions 226 has a higher electric potential than a portion of thedrift region beneath the JBS regions 230 in response to a forwardvoltage applied to the Schottky contact

FIG. 12 illustrates an exemplary mask layout for the p-type implantsthat define the JBS regions 230 and the subregions 226 for the device200 shown in FIG. 4.

While embodiments of the present invention have been described withreference to particular sequences of operations, as will be appreciatedby those of skill in the art, certain operations within the sequence maybe reordered while still benefiting from the teachings of the presentinvention. Accordingly, the present invention should not be construed aslimited to the exact sequence of operations described herein.

In the drawings and specification, there have been disclosed typicalembodiments of the invention and, although specific terms are employed,they are used in a generic and descriptive sense only and not forpurposes of limitation, the scope of the invention being set forth inthe following claims.

What is claimed is:
 1. A semiconductor device comprising: a drift layerhaving a first surface with an active region and a plurality of junctionbarrier element recesses, wherein the drift layer is doped with a dopingmaterial of a first conductivity type; a Schottky layer over the activeregion of the first surface to form a Schottky junction; and a pluralityof first doped regions that extend into the drift layer aboutcorresponding ones of the plurality of junction barrier element recesseswherein the plurality of first doped regions are doped with a dopingmaterial of a second conductivity type, which is opposite the firstconductivity type, and form an array of junction barrier elements in thedrift layer below the Schottky junction.
 2. The semiconductor device ofclaim 1 wherein each of the plurality of junction barrier elementrecesses has at least one side and a bottom and each of the plurality offirst doped regions extends into the drift layer about the at least oneside and the bottom of a corresponding one of the plurality of junctionbarrier element recesses.
 3. The semiconductor device of claim 1 whereinjunction barrier elements in the array of junction barrier elements areseparated from one another within the drift layer.
 4. The semiconductordevice of claim 1 wherein a depth of at least one of the plurality ofjunction barrier element recesses is at least 0.1 microns.
 5. Thesemiconductor device of claim 4 wherein a width of at least one of theplurality of junction barrier element recesses is at least 0.5 microns.6. The semiconductor device of claim 1 wherein a width of at least oneof the plurality of junction barrier element recesses is at least 0.5microns.
 7. The semiconductor device of claim 1 wherein the drift layeris further associated with an edge termination region that issubstantially laterally adjacent the active region and comprises an edgetermination structure.
 8. The semiconductor device of claim 7 whereinthe edge termination structure comprises a plurality of guard rings andthe first surface of the drift layer comprises a plurality of guard ringrecesses such that at least some of the plurality of guard rings aresecond doped regions that extend into the drift layer aboutcorresponding ones of the plurality of guard ring recesses, and thesecond doped regions are doped with the doping material of the secondconductivity type.
 9. The semiconductor device of claim 8 wherein guardrings in the plurality of guard rings are separated from each otherwithin the drift layer.
 10. The semiconductor device of claim 1 whereinthe Schottky layer is formed from a low barrier height capable metal.11. The semiconductor device of claim 10 wherein the low barrier heightcapable metal of the Schottky layer comprises at least one of a groupconsisting of titanium, chromium, and aluminum.
 12. The semiconductordevice of claim 1 wherein the drift layer comprises silicon carbide. 13.The semiconductor device of claim 1 wherein the drift layer and theSchottky layer are part of a Schottky diode.
 14. The semiconductordevice of claim 1 wherein the drift layer and the Schottky layer arepart of a silicon carbide Schottky diode.